As dynamic random access memory (DRAM) devices become more highly integrated, the area of the substrate available for each memory cell is reduced. A predetermined memory cell capacitance, however, should be maintained despite the reduced substrate area available to maintain a memory cell's reading capacity, reduce soft errors, and facilitate low voltage operation. Accordingly, there is a need to provide memory cell capacitors having a predetermined capacitance on a smaller surface area of a microelectronic substrate.
Techniques have been discussed to provide capacitor electrodes having increased surface areas on smaller portions of a microelectronic substrate. In particular, the surface area of a capacitor electrode can be increased by forming a hemispherical grained silicon (HSG-Si) layer on the electrode surface. For example, HSG silicon layers have been formed using native oxide film removal and high vacuum annealing techniques as discussed in the reference by H. Watanabe et al. entitled "An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes", SSDM, pp. 478-480,1991.
According to known HSG-Si fabrication techniques, however, the formation of the HSG-Si layer may result in undesired conductive paths between storage electrodes. In addition, the resulting HSG-Si layer may be insufficiently doped thus making it difficult to obtain a desired conductivity. Accordingly, it may be necessary to remove portions of the HSG-Si layer between storage electrodes. In particular, an etch-back step can be used to remove portions of the HSG-Si layer between the storage electrodes. The etch-back step, however, may damage portions of the HSG-Si layer on the storage electrodes and reduce a surface area thereof.
The dopant concentration of the HSG-Si layer can also affect the reliability of the resulting capacitor. In particular, an HSG-Si layer with an insufficient conductivity may result in an undesired variation in the C-V characteristics of the capacitor by lowering the ratio of Cmin to Cmax (Cmin/Cmax). For example, the capacitance may be at a minimum (Cmin) when a positive voltage is applied to a storage electrode with an insufficient concentration of an N-type dopant, and at a maximum (Cmax) when a negative voltage is applied to the storage electrode. Accordingly, the ratio of Cmin to Cmax may be reduced thus reducing the reliability of the capacitor.